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An Integrated System-Level Design for Testability Methodology [Elektronisk resurs]

Larsson, Erik, 1966- (författare)
Peng, Zebo (preses)
Linköpings universitet Institutionen för datavetenskap (utgivare)
Linköpings universitet Tekniska högskolan (utgivare)
Publicerad: Linköping : Linköping University Electronic Press, 2000
Engelska 282
Serie: Linköping Studies in Science and Technology. Dissertations, 0345-7524 0345-7524 ; 660
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  • E-bokAvhandling(Diss. Linköping : Linköpings universitet, 2000)
Sammanfattning Ämnesord
Stäng  
  • HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level. 

Ämnesord

Natural Sciences  (hsv)
Computer and Information Sciences  (hsv)
Information Systems  (hsv)
Naturvetenskap  (hsv)
Data- och informationsvetenskap  (hsv)
Systemvetenskap, informationssystem och informatik  (hsv)
SOCIAL SCIENCES  (svep)
Statistics, computer and systems science  (svep)
Informatics, computer and systems science  (svep)
Computer and systems science  (svep)
SAMHÄLLSVETENSKAP  (svep)
Statistik, data- och systemvetenskap  (svep)
Informatik, data- och systemvetenskap  (svep)
Data- och systemvetenskap  (svep)

Genre

government publication  (marcgt)

Indexterm och SAB-rubrik

Digital systems
Test design
System-on-chip
Hardware
Systems design
Testing
Dissertations
Hårdvara
Systemutveckling
Testning
Databehandling Systemutveckling
Inställningar Hjälp

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