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FältnamnIndikatorerMetadata
00017042cam a22006377a 4500
00113589482
003SE-LIBR
00520121219105949.0
008121114s2012 flua|||||b||||001 0|eng|c
020 a 9781439848357q hbk.
020 a 1439848351q hbk.
035 a (AuCNLKIN)z9utsy b2628373
040 a StDuBDSd Uange a
041 a eng
042 a ukblcatcopy
0820 4a 621.381522 22
084 a Pcib2 kssb/8 (machine generated)
2451 0a Nano-semiconductors :b devices and technology /c edited by Krzysztof Iniewski.
264 1a Boca Raton, Fla.b CRC ;a London :b Taylor & Francis [distributor],c c2012.
300 a xiv, 585 p.b ill.c 25 cm.
490a Devices, circuits, and systems.
504 a Includes bibliographical references and index.
505a Contents: pt. I Semiconductor Materials -- ch. 1 Electrical Propagation on Carbon Nanotubes: From Electrodynamics to Circuit Models / Giovanni Miano -- 1.1.Introduction -- 1.2.Electrodynamics of CNTs -- 1.2.1.Generality -- 1.2.2.Band Structure of a CNT Shell -- 1.2.3.Constitutive Relation for a CNT Shell -- 1.2.4.Number of Effective Channels for SWCNTs and MWCNTs -- 1.3.An Electromagnetic Application: CNTs as Innovative Scattering Materials -- 1.3.1.Generality -- 1.3.2.Electromagnetic Models for CNT Scattering -- 1.4.Circuital Application: CNTs as Innovative Interconnects -- 1.4.1.CNTs in Nanointerconnects -- 1.4.2.TL Model for a CNT Interconnect -- 1.4.3.A Bundle of CNTs as Innovative Chip-to-Package Interconnects -- 1.5.Conclusions -- References -- ch. 2 Monolithic Integration of Carbon Nanotubes and CMOS / Huikai Xie -- 2.1.Introduction -- 2.1.1.CNT Synthesis -- 2.1.2.CMOS-CNT Integration Challenges and Discussion --
505a Contents note continued: 2.2.CNT Synthesis by Localized Resistive Heating on Mock-CMOS -- 2.2.1.Microheater Design -- 2.2.2.Device Fabrication and Microheater Characterization -- 2.2.2.1.Device Fabrication -- 2.2.2.2.Microheater Characterization -- 2.2.3.Room Temperature CNT Synthesis -- 2.3.Maskless Post-CMOS CNT Synthesis on Foundry CMOS -- 2.3.1.Integration Principles and Device Design -- 2.3.2.Device Fabrication and Characterization -- 2.3.3.On-Chip Synthesis of CNTs -- 2.3.4.Characterization of CNTs and Circuit Evaluations -- 2.4.Conclusion -- References -- ch. 3 Facile, Scalable, and Ambient--Electrochemical Route for Titania Memristor Fabrication / Nathan M. Neihart -- 3.1.Introduction -- 3.2.Theory and Device Operation -- 3.3.Applications of Memristors -- 3.4.Current Memristive Materials and Fabrication Technologies -- 3.5.Memristor Fabrication via Electrochemical Anodization -- 3.6.Test Results of Electrochemical Anodization-Based Memristors -- 3.7.Conclusions --
505a Contents note continued: References -- ch. 4 Spin Transport in Organic Semiconductors: A Brief Overview of the First Eight Years / Sandipan Pramanik -- 4.1.Introduction -- 4.1.1.Spintronics in Data Storage -- 4.1.1.1.GMR Read Heads -- 4.1.1.2.Magnetic Random Access Memory -- 4.1.2.Spintronics for Information Processing -- 4.1.3.Organic Semiconductor Spintronics -- 4.2.Basic Elements of Spin Transport and Implications for Organics -- 4.2.1.Spin Injection -- 4.2.2.Spin Relaxation -- 4.2.2.1.Elliott-Yafet Mechanism -- 4.2.2.2.D'yakonov-Perel' Mechanism -- 4.2.2.3.Bir-Aronov-Pikus Mechanism -- 4.2.2.4.Hyperfine Interaction -- 4.2.3.Spin Relaxation in Organics: General Considerations -- 4.2.4.Measurement of Spin Relaxation Length and Time: Spin Valve Devices -- 4.3.Spin Injection and Transport in Organics: Spin Valve Experiments -- 4.3.1.Organic Thin Films -- 4.3.1.1.Sexithienyl (T6) Thin Films -- 4.3.1.2.Tris 8-Hydroxyquinoline Aluminum (Alq3) Thin Films -- 4.3.1.3.Other Organics --
505a Contents note continued: 4.3.2.Organic Nanowires -- 4.4.Spin Injection and Transport in Organics: Meservey-Tedrow Spin Polarized Tunneling, Two-Photon Photoemission (TPPE), and oSR Experiments -- 4.4.1.Meservey-Tedrow Spin Polarized Tunneling -- 4.4.2.TPPE Spectroscopy -- 4.4.2.1.Background -- 4.4.2.2.Spin Injection and Transport Studies by TPPE Spectroscopy -- 4.4.3.Low-Energy Muon Spin Rotation -- 4.4.3.1.Background -- 4.4.3.2.Measurement of Spin Diffusion Length in Organics by oSR Spectroscopy -- 4.5.Outlook and Conclusion -- 4.5.1.Nonvolatile Memory and Magnetic Field Sensors -- 4.5.2.Spin Based Classical and Quantum Computing -- 4.5.3.Spin Based OLEDs -- Acknowledgment -- References -- pt. II Silicon Devices and Technology -- ch. 5 SiGe BiCMOS Technology and Devices / Edward Preisler -- 5.1.Introduction -- 5.2.SiGe HBT Device Physics -- 5.3.Applications Driving SiGe Development -- 5.4.SiGe Performance Metrics -- 5.5.Device Optimization and Roadmap --
505a Contents note continued: 5.6.Modern SiGe BiCMOS RF Platform Components -- 5.7.Conclusions -- Acknowledgments -- References -- ch. 6 Ultimate FDSOI Multigate MOSFETs and Multibarrier Boosted Gate Resonant Tunneling FETs for a New High-Performance Low-Power Paradigm / Aryan Afzalian -- 6.1.Simulation Algorithm -- 6.2.Gate Coupling Optimization in Nanoscale Nanowire MOSFETs: Electrostatic Versus Quantum Confinement -- 6.3.Physics of RT-FET -- 6.3.1.Influence of Barrier Width -- 6.4.Schottky Barrier RT-FET -- 6.5.Conclusions -- Acknowledgments -- References -- ch. 7 Development of 3D Chip Integration Technology / Katsuyuki Sakuma -- 7.1.Introduction -- 7.2.3D Integration Technology -- 7.2.1.Advantages of 3D Chip Integration -- 7.2.2.Limitations of 3D Chip Integration -- 7.2.2.1.Thermal Management -- 7.2.2.2.Design Complexity -- 7.2.3.Various Kinds of 3D Technology -- 7.2.4.Approaches for 3D Integration -- 7.2.4.1.Bottom-Up Approach -- 7.2.4.2.Top-Down Approach --
505a Contents note continued: 7.2.5.Key Enabling Technologies for 3D Chip Integration -- 7.3.Through-Silicon Via -- 7.3.1.Processing Flow for TSV -- 7.3.2.Via Etching -- 7.3.3.Insulation Layer -- 7.3.4.Barrier and Adhesion Layer -- 7.3.5.Conductive Materials for TSV -- 7.4.Bonding Technologies -- 7.4.1.Overview of Bonding Technologies -- 7.4.2.IMC Bonding -- 7.4.2.1.Intermetallic System -- 7.4.2.2.Solder Materials for IMC Bonding -- 7.4.3.Characteristics of IMC Bonding -- 7.4.3.1.Test Vehicle for Mechanical Evaluation of IMC Bonding -- 7.4.3.2.Shear Strength -- 7.4.3.3.Shock Test Reliability -- 7.4.3.4.Cross-Section SEM and EDX Analysis -- 7.4.3.5.Thermal Cycle Testing with IMC Bonding -- 7.4.4.Fluxless Bonding -- 7.4.4.1.Ar Plasma Treatment -- 7.4.4.2.Vacuum UV Treatment -- 7.4.4.3.Formic Acid Treatment -- 7.4.4.4.Hydrogen Radical Treatment -- 7.4.4.5.Comparison of Surface Treatments -- 7.5.Die-to-Wafer Integration Technology -- 7.5.1.Die Yield of Stacking Processes --
505a Contents note continued: 7.5.2.Die Cavity Technology -- 7.5.3.Alignment Accuracy -- 7.5.4.Test Vehicle: Design and Features -- 7.5.5.Results of Stacking Using Die Cavity Technology -- 7.5.6.Electrical Tests -- 7.6.Underfill Encapsulation for 3D Integration -- 7.6.1.Overview of Underfill Process -- 7.6.2.Vacuum Underfill Process -- 7.6.3.Results of Vacuum Underfill for 3D Chip Stack -- 7.7.Summary -- Acknowledgments -- References -- ch. 8 Embedded Spin-Transfer-Torque MRAM / Kangho Lee -- 8.1.Introduction -- 8.1.1.Motivation for Embedded STT-MRAM: Application Perspectives -- 8.1.2.Recent Industrial Efforts for MRAM Development -- 8.2.Magnetic Tunnel Junction: Storage Element of STT-MRAM -- 8.2.1.Magnetization Dynamics in Ferromagnetic Metals -- 8.2.2.Tunneling Magnetoresistance Ratio -- 8.2.3.Energy Barrier for Data Retention -- 8.2.4.Spin-Transfer-Torque (STT Switching) -- 8.3.1T-1MTJ STT-MRAM BITCELL -- 8.3.1.Read Margin -- 8.3.2.Write Margin --
505a Contents note continued: 8.4.MTJ Material Engineering for Write Power Reduction -- 8.4.1.Perpendicular Magnetic Anisotropy -- 8.4.2.Damping Constant and STT Efficiency -- References -- ch. 9 Nonvolatile Memory Device: Resistive Random Access Memory / Qingqing Sun -- 9.1.Introduction -- 9.1.1.Resistive Random Access Memory: History and Emerging Technology -- 9.1.2.Challenge for RRAM on Storage-Class Memory -- 9.1.2.1.Performance Requirement -- 9.1.3.Architecture Requirement -- 9.2.BTMO-Based RRAM -- 9.2.1.Device Fabrication and Current-Voltage Characterization -- 9.2.1.1.Device Fabrication -- 9.2.1.2.Current-Voltage Characterization -- 9.2.2.BTMO RRAM Integration for Embedded Application on 0.18 om Al Process and 0.13 om Cu Process -- 9.2.2.1.RRAM Integration on 0.18 om Al Process -- 9.2.2.2.RRAM Integration on 0.13 om Cu Process -- 9.2.3.Doping Effect in BTMO RRAM -- 9.2.4.Role of Compliance Current -- 9.2.5.Physical Mechanism and Its Evidence --
505a Contents note continued: 9.3.Memristor -- 9.3.1.Leon Chua's Theory of Fourth Fundamental Element -- 9.3.2.HP Laboratories' Discovery of Prototype Pt/TiO2-x/TiO2/Pt Memristor -- 9.4.Conclusion -- References -- ch. 10 DRAM Technology / Myoung Jin Lee -- 10.1.Introduction to Dynamic Random Access Memory -- 10.1.1.DRAM Cell -- 10.1.2.Sense Operation -- 10.2.Sensing Margin in DRAM -- 10.2.1.Definition of Sensing Margin -- 10.2.2.Noise Effect on Sensing Margin -- 10.2.2.1.DRAM Cell Performance (Leakage and Current Drivability) -- 10.2.2.2.High-Performance DRAM Cell Structures -- 10.2.2.3.VTH Mismatch in BLSA -- 10.2.2.4.Sensing Noise in Accordance with Data Pattern -- 10.2.3.Relation between Refresh Time and Sensing Noise in Accordance with Data Pattern -- 10.2.4.How to Improve Sensing Margin -- 10.2.4.1.Offset Compensation Sense Amplifier -- References -- ch. 11 Monocrystalline Silicon Solar Cell Optimization and Modeling / Victor Moroz -- 11.1.Introduction --
505a Contents note continued: 11.2.Modeling Optical Effects -- 11.2.1.Textured Surface -- 11.2.2.Behavior of Different Light Wavelengths -- 11.2.3.Optical Performance of Regular Surface Patterns -- 11.2.4.Regular versus Random Texture -- 11.3.Modeling Electronic Effects -- 11.3.1.Definition of Simulation Cell Structure -- 11.3.1.1.Structure Definition -- 11.3.1.2.Meshing Strategy -- 11.3.2.Modeling Methodology -- 11.3.2.1.Impact of Optical Reflectivity on Optically Generated Carrier Profile -- 11.3.2.2.Surface Recombination Rate -- 11.3.2.3.Contact Resistance -- 11.3.2.4.Bulk Recombination -- 11.3.3.Current Crowding -- 11.3.4.Optimizing Efficiency of Solar Cell -- 11.3.5.Comparing 3D with 2D and 1D -- 11.3.6.Junction Optimization -- 11.4.Conclusions -- References -- ch. 12 Radiation Effects on Silicon Devices / Alessandro Paccagnella -- 12.1.Introduction -- 12.2.Radiation Environments -- 12.2.1.Space -- 12.2.2.Terrestrial Environment -- 12.2.3.Man-Made Radiation -- 12.3.TID EFFECTS --
505a Contents note continued: 12.3.1.MOSFETs -- 12.3.2.Bipolar Devices -- 12.4.Displacement Damage -- 12.4.1.Charge-Coupled Devices -- 12.5.Single Event Effects -- 12.5.1.Single Event Upsets in SRAMs -- 12.5.2.SEEs in Flash Cells -- 12.6.Conclusions -- References -- pt. III Compound Semiconductor Devices and Technology -- ch. 13 GaN/InGaN Double Heterojunction Bipolar Transistors Using Direct-Growth Technology / Russell Dean Dupuis -- 13.1.Introduction -- 13.2.GaN/InGaN HBT Design -- 13.3.GaN/InGaN HBT Epitaxial Growth and Fabrication Techniques -- 13.4.State-of-the-Art Direct-Growth GaN/InGaN DHBTs -- 13.4.1.Impact of Indium in InGaN Base Layer -- 13.4.2.Burn-In Effect -- 13.4.3.High-Performance GaN/InGaN DHBT -- 13.5.Technology Development Trends for III-N HBTs -- References -- ch. 14 GaN HEMTs Technology and Applications / Subramaniam Arulkumaran -- 14.1.Introduction -- 14.2.Device Types and Structures -- 14.2.1.Conventional GaN HEMTs with Cap Layer -- 14.2.2.Advanced GaN HEMTs --
505a Contents note continued: 14.2.2.1.HEMTs with A1N Spacer Layer -- 14.2.2.2.Double Heterostructure HEMTs -- 14.2.2.3.Lattice Matched InA1N/GaN HEMTs -- 14.2.2.4.Quaternary Barrier HEMTs -- 14.2.2.5.N-Face GaN/AlGaN HEMTs -- 14.2.2.6.Field Plate Assisted GaN HEMTs -- 14.2.2.7.GaN Metal-Insulators-Semiconductor HEMTs -- 14.3.Device Fabrication -- 14.3.1.Mesa Isolation -- 14.3.2.Ohmic-Contact Formation -- 14.3.3.Gate Formation by EBL -- 14.3.4.Device Passivation -- 14.3.5.Substrate Thinning and Via-Hole Formation -- 14.4.Device Performance -- 14.4.1.Effects of Passivation -- 14.4.1.1.DC and Pulse I-V Characteristics -- 14.4.1.2.RF Characteristics -- 14.4.2.Temperature-Dependent Characteristics -- 14.4.2.1.DC Characteristics -- 14.4.2.2.RF Characteristics -- 14.5.GaN HEMT Applications -- 14.5.1.GaN Hybrid Amplifiers -- 14.5.2.GaN MMICs -- References --
505a Contents note continued: ch. 15 Surface Treatment, Fabrication, and Performances of GaN-Based Metal-Oxide-Semiconductor High-Electron Mobility Transistors / Ching-Ting Lee -- 15.1.Introduction -- 15.2.Ohmic Contacts on GaN-Based Semiconductors -- 15.3.Gate Oxides: Materials and Deposition Methods -- 15.4.Surface Treatment of GaN-Based Semiconductors -- 15.4.1.Sulfidation Method -- 15.4.2.Chlorination Method -- 15.4.3.PEC Method -- 15.5.GaN-Based Metal-Oxide-Semiconductor Devices -- 15.6.GaN-Based MOSHEMTs -- 15.7.Conclusions -- References -- ch. 16 GaN-Based HEMTs on Large-Diameter Si Substrate for Next Generation of High Power/High Temperature Devices / Farid Medjdoub -- 16.1.Introduction -- 16.2.GaN-on-Si Devices for High Power at High Frequency -- 16.2.1.DC Characteristics -- 16.2.2.Dynamic Characteristics -- 16.3.GaN on Silicon Devices for Harsh Environment -- 16.4.GaN Power Transistors on Silicon Substrate for Switching Application --
505a Contents note continued: 16.4.1.Ultrathin Barrier Device Design and Fabrication -- 16.4.2.Results and Discussion -- 16.5.Reliability Aspects -- 16.5.1.Thermal Stability Enhancement via In Situ Si3N4 Cap Layer -- 16.5.2.Reliability Test on Power Switching Devices -- 16.5.2.1.Device and Test Description -- 16.5.2.2.Off-State Stress -- 16.5.3.Reliability Test on RF Devices -- 16.6.Conclusions -- References -- ch. 17 GaAs HBT and Power Amplifier Design for Handset Terminals / Kazuya Yamamoto -- 17.1.Introduction -- 17.2.Basics of GaAs-Based HBTs -- 17.2.1.Principle of Operation -- 17.2.2.DC and RF Characteristics -- 17.2.3.Role of Ballasting Resistors and VSWR Ruggedness -- 17.3.Linear Power Amplifier Design for Handset Terminals -- 17.3.1.Basic Bias Circuit Topology -- 17.3.2.Bias Drive and AM-AM/AM-PM Characteristics -- 17.3.3.Bias Circuits and AM-AM/AM-PM Characteristics -- 17.3.4.Harmonic Terminations and AM-AM/AM-PM Characteristics --
505a Contents note continued: 17.3.5.Circuit Design Example for Two-Stage Power Amplifier -- 17.4.Summary -- References -- ch. 18 Resonant Tunneling and Negative Differential Resistance in III-Nitrides / Vladimir Litvinov -- 18.1.Introduction -- 18.2.Single-Layer Devices -- 18.3.Resonant Tunneling Diodes -- 18.3.1.Current-Voltage Characteristics -- 18.4.Superlattices -- 18.4.1.Domain Oscillations and SL-Based High Frequency Sources -- 18.4.2.Conduction Band Profile and Field-Mobility Relation -- 18.4.3.Circuit Design -- 18.4.4.Traveling Electrical Domains -- 18.4.5.Power Oscillations and Their Spectral Content -- 18.4.6.Power Efficiency -- 18.5.Fabrication and DC Characterization of AlxGa1-xN/GaN SL Diodes -- Acknowledgment -- References -- ch. 19 New Frontiers in Intersubband Optoelectronics Using III-Nitride Semiconductors / Eva Monroy -- 19.1.Introduction to ISB Optoelectronics -- 19.2.III-Nitride Materials for Near-IR Optoelectronics -- 19.2.1.Electronic Structure --
505a Contents note continued: 19.2.2.Growth and Structural Properties -- 19.2.3.Optical Characterization -- 19.2.3.1.IB Characterization -- 19.2.3.2.ISB Absorption -- 19.2.4.Polarization-Induced Doping -- 19.2.5.GaN/A1N Quantum Dots -- 19.2.6.A1InN/GaN System -- 19.2.7.Semipolar III-Nitrides -- 19.2.8.Cubic III-Nitrides -- 19.3.Devices Operating in Near-IR -- 19.3.1.All-Optical Switches -- 19.3.2.Infrared Photodetectors -- 19.3.3.Electro-Optical Modulators -- 19.3.4.Toward Light Emitters -- 19.4.Toward Longer Wavelengths -- 19.5.Conclusions and Perspectives -- References.
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650 7a Halvledare0 https://id.kb.se/term/sao/Halvledare2 sao
650 0a Semiconductors.
650 0a Nanoelectromechanical systems.
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